Two significant advantages of the PCI bus over its predecessor (VL-Bus), are that it can run out of synch with the CPU, and that it can fully utilize Plug and Play technology. With enhanced arbitration, the PCI bus is capable of bus mastering, which is where the VL-Bus failed.
The PCI bridge/controller acts as a buffer between the CPU and the devices on the PCI bus, which allows the CPU to process other tasks, versus waiting for the PCI device, thus eliminating wait states. All com-munication to the CPU from a PCI device takes place through the NorthBridge (PCI controller).
A wait state takes place when the CPU attempts to access data in DRAM while it is being refreshed by the memory controller.
The typical 4 slot PCI bus uses its own internal interrupt system for dealing with requests from the de-vices on the bus, which are referred to as; interrupts ‘INTA, INTB, INTC, and INTD, or A, B, C, D. These 4 ‘virtual’ interrupts are mapped to interrupts IRQ9 through IRQ12.
If there are more than 4 slots, or USB is being utilized then two devices share an IRQ. These interrupts may be viewed by the A+ technician in the BIOS set up screen.
When data in the PCI bus has consecutive addresses it is grouped into packets and sent as a single burst, independent of the CPU, which is referred to as burst mode.
The inherent design of the PCI bus was to support the ISA bus and not necessarily replace it.on statement at Testbusters.net is to see that you pass your exam, first try, painlessly, and economically, while learning!
